1. Technical Field
The present invention relates to integrated circuit (IC) chip design and, more particularly, to methods of designing buffer placement in an IC chip.
2. Description of Related Art
Buffer insertion has become a critical step in deep submicron design as interconnect now plays a dominating role in determining system performance. The insertion of buffers and inverters on signal nets can provide several advantages, including reducing interconnect delay, restraining noise, improving the slew rate, and fixing electrical violations. Current designs easily require thousands of nets to be buffered, and it is speculated that close to 800,000 buffers will be required for chip designs in 70 nanometer technology for a microprocessor chip with 500 million transistors.
Achieving timing closure becomes more difficult when buffer insertion is deferred to the back end of the design process, and the buffers must be squeezed into whatever left over space remains. The problem is particularly acute for custom designs, where large IP core macros and custom data flow structures are present, blocking out significant areas from buffering possibilities. Application Specific Integrated Circuit (ASIC) designs can also run into similar headaches if they are dense, or have locally dense hot spots.
To manage the large number of buffers and also achieve high performance on the critical global nets, buffers must be planned for early in the design, so that the rest of the design flow is aware of the required buffering resources. In addition, design routability has also become a critical problem; one must make sure that an achievable routing solution exists during the physical floorplanning stage. Thus, global wiring must be planned early to minimize routing congestion, hot spots, and crosstalk problems later on in the flow.
In response to the need for an interconnect-centric design methodology, a new body of research on buffer block planning has recently established itself in the literature. These works focus on “physical-level interconnect planning.”. Many have proposes the creation of additional buffer blocks to be inserted into an existing floorplan. These buffer blocks are essentially top-level macro blocks containing only buffers. One proposed implementation of this method is the construction of these blocks using feasible regions. A feasible region is the largest polygon in which a buffer can be inserted for a particular net such that the net's timing constraint is satisfied. Others have added a notion of independence to the feasible regions while also trying to relieve routing congestion during optimization. Still others propose an optimal buffer block planning algorithm in terms of maximizing the number of inserted buffers (assuming that one buffer is sufficient for each net). Finally, still others present a multi-commodity flow-based approach to buffering 2-pin nets assuming that a buffer block plan had already been created. This approach has been extended to multi-pin nets in.
With reference now to FIG. 1, a diagram showing the result of buffer block planning based on physical-level interconnect planning on a circuit is depicted in accordance with the prior art. The buffer blocks 121–133 are indicated by dashes in between macro functional blocks 101–110. Observe that buffers 121–133 are essentially packed between larger existing floorplanned functional blocks 101–110. There are two fundamental problems with this buffer block planning approach:    I. Since buffers are used to connect global wires, there will considerable contention for routing resources (i.e. the number of wiring tracks) in the regions between macro functional blocks 101–110. For any given rectangular region, there are a fixed number of wiring tracks that can be used in that region. Thus, only a fixed number of wires can go through the region. As more and more wires are needed, it is the routing resources that become contentious. Therefore, the design may not be routable due to heavy congestion between functional blocks 101–110.    II. Buffers must be placed in poor locations since better locations are blocked. Some functional blocks 101–110 may even be so large that routing over the functional block 101–110 is infeasible, even if buffers are inserted immediately before and after the functional block 101–110. For example, signal integrity could degrade beyond the point of recovery or wire delay may simply be too high. One may be able to alleviate the problem by using wider wires on thick metal, powering up to very large buffers, etc., but these solutions exacerbate the congestion problem.
The flaws are not with buffer block planning per se; rather, it is certainly a reasonable method for pre-planning buffers within current design flows. However, buffer block planning is really an interconnect-centric idea being applied to a device/logic-centric flow. Ultimately this methodology will not be sustainable as design complexity continues to increase. A different methodology is required.
Ideally, buffers should be dispersed with some regularity throughout the design. Clumping buffers together, e.g., in buffer blocks, or between abutting macros invites routing headaches. A more uniform distribution of buffers will also naturally spread out global wires. Therefore, a method of buffer block design that allows placement of buffers within functional blocks is desirable.